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ResistorTransistor Logic 

Consider the most basic transistor circuit, such as the one shown to the left. We will only be applying one of two voltages to the input I: 0 volts (logic 0) or +V volts (logic 1). The exact voltage used as +V depends on the circuit design parameters; in RTL integrated circuits, the usual voltage is +3.6v. We'll assume an ordinary NPN transistor here, with a reasonable dc current gain, an emitterbase forward voltage of 0.65 volt, and a collectoremitter saturation voltage no higher than 0.3 volt. In standard RTL ICs, the base resistor is 470Ω and the collector resistor is 640Ω.
When the input voltage is zero volts (actually, anything under 0.5 volt), there is no forward bias to the emitterbase junction, and the transistor does not conduct. Therefore no current flows through the collector resistor, and the output voltage is +V volts. Hence, a logic 0 input results in a logic 1 output.
When the input voltage is +V volts, the transistor's emitterbase
junction will clearly be forward biased. For those who like the
mathematics, we'll assume a similar output circuit connected to this
input. Thus, we'll have a voltage of 3.6  0.65 = 2.95 volts applied
across a series combination of a 640Ω output resistor and a
470Ω input resistor. This gives us a base current
of:_{ }
With a logic 1 input, then, this circuit produces a logic 0 output. We have already seen that a logic 0 input will produce a logic 1 output. Hence, this is a basic inverter circuit.
As we can see from the above calculations, the amount of current provided to the base of the transistor is far more than is necessary to drive the transistor into saturation. Therefore, we have the possibility of using one output to drive multiple inputs of other gates, and of having gates with multiple input resistors. Such a circuit is shown to the right.
In this circuit, we have four input resistors. Raising any one input to +3.6 volts will be sufficient to turn the transistor on, and applying additional logic 1 (+3.6 volt) inputs will not really have any appreciable effect on the output voltage. Remember that the forward bias voltage on the transistor's base will not exceed 0.65 volt, so the current through a grounded input resistor will not exceed 0.65v/470Ω = 1.383 ma. This does provide us with a practical limit on the number of allowable input resistors to a single transistor, but doesn't cause any serious problems within that limit.
The RTL gate shown above will work, but has a problem due to possible signal interactions through the multiple input resistors. A better way to implement the NOR function is shown to the left.
Here, each transistor has only one input resistor, so there is no interaction between inputs. The NOR function is performed at the common collector connection of all transistors, which share a single collector load resistor.
This is in fact the pattern for all standard RTL ICs. The very commonlyused µL914 is a dual twoinput NOR gate, where each gate is a twotransistor version of the circuit to the left. It is rated to draw 12 ma of current from the 3.6V power supply when both outputs are at logic 0. This corresponds quite well with the calculations we have already made.
Standard fanout for RTL gates is rated at 16. However, the fanin for a standard RTL gate input is 3. Thus, a gate can produce 16 units of drive current from the output, but requires 3 units to drive an input. There are lowpower versions of these gates that increase the values of the base and collector resistors to 1.5K and 3.6K, respectively. Such gates demand less current, and typically have a fanin of 1 and a fanout of 2 or 3. They also have reduced frequency response, so they cannot operate as rapidly as the standard gates. To get greater output drive capabilities, buffers are used. These are typically inverters which have been designed with a fanout of 80. They also have a fanin requirement of 6, since they use pairs of input transistors to get increased drive.
We can get a NAND function in either of two ways. We can simply invert the inputs to the NOR/OR gate, thus turning it into an AND/NAND gate, or we can use the circuit shown to the right.
In this circuit, each transistor has its own separate input resistor, so each is controlled by a different input signal. However, the only way the output can be pulled down to logic 0 is if both transistors are turned on by logic 1 inputs. If either input is a logic 0 that transistor cannot conduct, so there is no current through either one. The output is then a logic 1. This is the behavior of a NAND gate. Of course, an inverter can also be included to provide an AND output at the same time.
The problem with this NAND circuit stems from the fact that transistors are not ideal devices. Remember that 0.3 volt collector saturation voltage? Ideally it should be zero. Since it isn't, we need to look at what happens when we "stack" transistors this way. With two, the combined collector saturation voltage is 0.6 volt  only slightly less than the 0.65 volt base voltage that will turn a transistor on.
If we stack three transistors for a 3input NAND gate, the combined collector saturation voltage is 0.9 volt. This is too high; it will promote conduction in the next transistor no matter what. In addition, the load presented by the upper transistor to the gate that drives it will be different from the load presented by the lower transistor. This kind of unevenness can cause some odd problems to appear, especially as the frequency of operation increases. Because of these problems, this approach is not used in standard RTL ICs.


 
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