Frequency division by an odd number is also possible. The circuit to the left is a demonstration of a divide-by-3 counter. No gates are required to control the sequence if JK flip-flops are used; feeding the output signals back to the appropriate inputs is sufficient.

Of course, it is not possible to get a symmetrical (50% duty cycle) square wave with this circuit. The A output is at logic 1 for two clock pulses out of three; the B output is at logic 1 for one clock pulse out of three. Thus, duty cycles of 1/3 (33.333%) and 2/3 (66.667%) are available.

This rendition of a divide-by-5 counter actually follows the normal decimal (or binary) count from zero through four. The primary control feature is the feedback from the C' output to flip-flop A's J input. This feedback prevents flip-flop A from switching from logic 0 to logic 1 in an effort to go from a count of four to a count of five. At the same time, the C output is applied to flip-flop C's K input to force flip-flop C to reset on the next clock pulse.

This particular arrangement is often combined with a single flip-flop in an IC package. The combination can then be used either as a normal decimal counter or as a divide-by-10 counter with a true square-wave output.

If it is not necessary to maintain a standard binary counting sequence, we can often interconnect the flip-flops so as to eliminate the need for any extra gates, as shown to the left. Note that the K inputs to both flip-flops A and B are connected to logic 1. As a result, outputs A and B will remain at logic 1 for only one clock pulse at a time, and will then reset to logic 0. Output C will toggle after B goes to logic 1.

Output C has a 40% duty cycle. Outputs A and B produce two output pulses for each pulse from C, but not at equal intervals. The counting sequence is 0, 1, 2, 5, 6, 0, etc.

This counter circuit actually has a flaw as shown: if it powers up in state 4 (A = 0, B = 0, C = 1), it will remain in that state and be unable to change at all. To correct this, we can disconnect C's K input from output B, and connect it to output A' instead. Now the first clock pulse will force the circuit to state 0 (000), from which the count will proceed normally. This change will not affect the normal counting sequence, because a logic 1 at the K input cannot prevent the flip-flop from changing to a logic 1, and would force C back to a logic 0 at the same time it would change anyway.