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| D Flip-Flop Using NOR Latches | D Flip-Flop Using NAND Latches | CMOS Flip-Flop Construction |

D Flip-Flop Using NOR Latches

This circuit utilizes three interconnected RS latch circuits, as shown. This example uses NOR gates, but NAND gates can easily be used to perform the same function.

The two input latch circuits essentially store the D and D' signals separately, and apply those stored signals to the output latch. While the CLK input is a logic 0, changes to the D input can only affect the state of the lower gate of the lower input latch circuit. The other gates are locked into their output states by their other interconnections.

When CLK goes to logic 1, it inherently forces the outputs of the two middle input gates to logic 0. This effectively isolates the output latch from any input changes. Note that at this time, one or the other of the two input latches will be in an illegal state, depending on the state of the D input. This illegal state overrides the latching action of that input circuit.

Now, when CLK falls to logic 0, whichever input latch was in an illegal state will abruptly resume its latching action, and will at once control the state of the output latch. In this manner, the circuit is still an edge-triggered flip-flop that will take on the state of the D input at the moment of the falling clock edge.







Edge-triggered D NOR flip-flop

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