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### Circuit Description

At first glance, the circuit shown to the right seems very strange. The collecor loads for Q1 and Q2 actually consist of two separate current mirrors, one using Q1 for its reference current, and the other using Q2. At first glance, you might get the idea that the two mirrors cancel each other out and prevent the circuit from generating any output signal. Fortunately, this is not the case.

The first thing to note is that with Q5 and Q8 both connected as diodes, the output voltages at OUT1 and OUT2 are pretty well fixed at VCC - VBE(PNP). This means no signal voltage at the outputs; the output signals will consist of current only. Therefore we need to look at the output currents under assorted conditions.

The second point about this circuit is that the reference current for Q5 is not simply IC1. If we ignore the base currents for Q5 through Q8 as being negligible and assume that the mirrors are perfectly matched, we find that the following equations must hold:

 IC1 = IC5 + IC7 + IOUT1 IC2 = IC6 + IC8 + IOUT2 IC6 = IC5 IC7 = IC8

Looking at the equations above, we might initially think that the Lee Load could permit all of IC1 to become the reference current for Q5, so that Q6 then takes all of IC2 (assuming the inputs are fully balanced). This would leave no current for Q8, and hence none for Q7. Or, the reverse could be true, or any state between those two extremes. In practice, this will not occur. Even though the amount of base current for Q5 through Q8 is very small, there is always a small amount of it. This keeps all four load transistors in an active state, so all will conduct some current. From there, values of rOUT for these transistors will cause a balancing effect to take place, so that the load collector currents will tend to even out. As a result, when the inputs are balanced so that IC1 = IC2, half of IC1 becomes IREF for Q5 (plus a slight amount for base currents of Q5 and Q6). The other half will be the mirrored current which is IC7. On the other side of the circuit, IC2 is split the same way, between IREF for Q8 and IC6. All of the collector current for both Q1 and Q2 is exactly taken by the load transistors, so there is no output current from either output.

Now let's see what happens if we adjust IN1 to increase IC1 by a small increment, which we will call ΔIC. (You can assume a quiescent IC1 of 1 mA and a ΔIC of 0.01 mA if you want a concrete example; the results will be the same either way.) We will initially assume no connections to OUT1 or OUT2, so there will be no current through these points in the circuit. Of course, all resulting changes happen in a very small fraction of a second, but we'll look at them in sequence, as if they happened one at a time, and see where that leads us:

1. IC7 hasn't changed yet, so IC5 increases by ΔIC.
2. This causes IC6 to also increase by ΔIC.
3. At the same time, since Q4 supplies a constant current to Q1 and Q2 together, IC2 decreases by ΔIC.
4. The combination of the increase in IC6 and the decrease in IC2 reduces the available current to Q8, so IC8 is reduced by 2ΔIC.
5. This in turn means that IC7 is reduced by 2ΔIC.
6. IC1 hasn't changed any further, so IC5 must now increase by 2ΔIC, which means a total increase of 3ΔIC.
7. This change in turn propogates around the loop, causing further changes in the same direction.

This sequence amounts to positive feedback that rapidly locks up the circuit once the inputs become unbalanced. Clearly the output terminals must be connected somewhere, such that these changes in IC1 and IC2 will be absorbed by the next circuit block.

It is also clear that the two current mirrors of the Lee Load must always be balanced. That is, IC5 = IC8 at all times. We know they are the same when the inputs are balanced and IC1 = IC2, and we have seen above that any imbalance will be immediately amplified to the point where the whole circuit will lock up. This in turn requires that:

1. IOUT1 = ΔIC
2. IOUT2 = -ΔIC

The above equations show that the current gain provided by this amplifier stage is the same as would be provided by transistors Q1 and Q2 standing alone. At the same time, keep in mind that with Q5 and Q8 connected as diodes, this amplifier stage provides essentially no output signal voltage at all.

### Common Mode Rejection

The obvious next question is, "Why bother using an amplifier stage with a Lee Load?" We could easily replace this whole stage with two simple emitter followers. That would give us about the same current gain, plus a unity signal voltage gain. What benefit does the Lee Load grant that justifies using it?

The answer lies in the difference between common mode gain and differential gain. We've already noted that there is no signal voltage output to speak of, and that applies to both common mode and difference mode signals. This circuit also produces very little common mode current output, although it does show a difference mode current gain.

In fact, where other differential amplifier circuits show a common mode gain of approximately unity, this circuit reduces common mode gain, typically by around two orders of magnitude (a factor of 0.01) The result is a very high common mode rejection ratio (CMRR), which is almost impossible to obtain any other way. Therefore, this circuit is commonly used in applications and devices where very high common mode rejection is required.

In practice, the stage with a Lee Load will typically be followed by a second amplifier stage with a current mirror load, with minimal connecting circuitry to allow for the needed dc voltage level shift. This combines the advantages of both circuits.

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